Physical Design Engineer

Job Responsibilities

• Responsible for ASIC/SoC physical implementation from netlist to GDSII, including floorplanning, power planning, physical synthesis, clock tree synthesis (CTS), place-and-route, physical verification, and tapeout.
• Perform timing closure and optimization to meet PPA (Performance, Power, Area) targets.

Qualifications

Required

• Solid experience in ASIC/SoC Physical Design and implementation flow.
• Proficient with Synopsys tools (ICC2 or Fusion Compiler, PrimeTime) and/or Cadence tools (Innovus, Tempus).
• Hands-on experience with netlist-to-GDSII flow, including floorplanning, power grids, clock tree synthesis, place & route, and physical verification.
• Strong knowledge of timing closure, signal integrity, crosstalk analysis, and IR drop analysis.
• Experience with FinFET technology nodes is required.

Preferred

• Experience with hierarchical implementation and full-chip integration.
• Familiarity with low-power design methodologies (UPF/CPF).
• Programming and scripting skills in Tcl, Perl, Python, C/C++, or Tk.
• Experience with web development technologies such as HTML, CSS, and JavaScript is a plus.