Python, Tcl

Python, Tcl

Tcl, Python, Perl, Develop and enhance entire timing closure flow from frontend pre-layout to backend post-layout, formal verification, STA for hierarchical design, Implement chip partition and floorplan, Function eco creation, Timing closure for both partition and full chip level, Synthesis Netlist quality check, Flow automation development, Constraints creation and validation timing budget

Tcl Scripting, Mentor EDA tools