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Job Description
The VLSI Physical Design Engineer is responsible for implementing and optimizing the layout of integrated circuits (ICs) from netlist to GDSII. This role plays a key part in turning high-level logic designs into manufacturable silicon chips, ensuring electrical performance, area, and power (PPA) goals are met, and the physical verification results are good.
Key Responsibilities
- Derive full-chip and block-level physical design from netlist to tape-out (netilst to GDSII).
- Floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and layout verifications.
- Work closely with front-end design, DFT, and package teams to ensure design closure.
- Sign-off on signal integrity, power integrity, reliability and manufacturability including performing static timing analysis (STA), IR drop analysis, EM analysis, and physical verification (DRC/LVS/DFM).
- Analyze, optimize and resolve congestion, timing, power integrity and signal integrity issues.
- Create and maintain physical design automation Tcl scripts, and flows development for design implementation.
- Interface with EDA tool vendors and foundries to ensure design compliance and manufacturability.
Job Requirements
- Minimum Master degree majoring in EE/CE/CS related fields.
- At least 2 years 7 years of experiences in VLSI field for designer and manager positions, respectively.
- Experience in tapeout with multi-million gates count SOC design, 10/7/5/3nm design experience is a plus.
- Solid skill sets of one of Cadence/Synopsys/Mentor EDA tools.
- Experience in design methodology, flow deployment/refinement and problem solving skill.
- Familiar with Perl/TCL scripting is a plus
- Proficiency in speaking and writing English is a plus.
- Good communication skill, team spirit, initiative, innovative and fast learning.
