Search by job, company or skills
Job description:
Validate HDL debug tools, test automatically script handling and help customers to clarify issues, even find workaround solutions.
Requirement:
1. MS degree or above with EE or CS background
2. Understand Verilog/VHDL or has 2+ years-experience in HDL design.
3. The experience of HDL simulator/debug tool verification is plus.
4. Familiar with Linux environment or scripts.
Date Posted: 26/09/2025
Job ID: 127232629