SOC Verification-Data (Shanghai)

1. Build a verification UVM environment and be familiar with automated and reusable development environments 2. Be familiar with and execute test plans for coverage targets and be familiar with performance verification, power consumption-aware simulation, RTL/FW co-simulation and GTL simulation 3. Be able to assist designers in debugging design defects, proficiently analyze verification modules, and improve and perfect the verification process.

1. 5 years of bachelor's degree in electronics, microelectronics, computer and other related majors, 3 years of SOC verification work experience as a master's degree or above 2. In-depth understanding of UVM, system Verilog, Makefile, Perl, Python and C/C++ 3. In-depth understanding of RISC-V/ARM processor architecture and AMBA4/5 protocol 4. Experience with chip interconnect protocols such as CXL and CCIX is preferred 5. Be serious and responsible in work, have good communication and learning abilities, strong English reading and writing skills, and good teamwork spirit.