Position Overview: We are seeking an experienced Packaging Engineer to drive the development of next-generation, high-performance semiconductor packaging solutions. This role focuses on the implementation of high-density interconnects and advanced system-in-package architectures. The candidate will be responsible for ensuring superior signal integrity and manufacturing scalability for complex electronic systems. Key Responsibilities .Advanced Substrate Layout: Lead the layout design of high-density substrates (including ABF), ensuring optimal routing for high-performance and high-I/O EICs. .Analog Signal Integrity: Optimize package designs for analog signal processing, ensuring minimal noise and high-fidelity signal transmission across the packaging interface. .Interconnect Process Development: Develop and qualify UBM (Under Bump Metallization) and uBump (micro-bump) processes for ultra-fine pitch flip-chip assembly. .EIC Integration: Lead the integration of high-I/O EICs into advanced packages, focusing on process stability, interconnect reliability, and complex die-to-die connectivity. .Foundry & Process Management: Drive advanced packaging workflows (such as ABF packaging), from material selection and DFM rules to final assembly and reliability qualification. Qualifications .PhD/MSc in Electrical Engineering, Microelectronics, Materials Science, or a related field. .3+ years experience in advanced semiconductor packaging or substrate design. .Technical experience in analog signal processing and signal integrity within a packaging environment. .Hands-on experience or deep knowledge of ABF layout design and ABF packaging processes. .Proven expertise in UBM and uBump (micro-bumping) technologies. .Preferred: Experience with high-I/O EIC integration for advanced computing or communication modules. .Background knowledge of Si photonics is preferred
