Senior Memory Design Engineer
Senior Memory Design Engineer
Broadcom4-7 Years
- Posted 2 days ago
- Be among the first 10 applicants
Job Description
Job Description:
JD for Senior Design Engineer
JD for Senior Design Engineer
- Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies
- Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
- Development of critical path and characterization flow to perform detailed margin and characterization simulations.
- Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off
- Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
- Logic simulations and detailed timing analysis of key paths in high speed memory design.
- Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.
- Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits
- Experience in Designing and driving one or many Memory Compilers Specifications to final release
- Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design
- Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.
- Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc
- Experience in Skill/Perl/Python Scripting is a strong plus
- Experience in Understanding the layout design issues in sub nanometer regime is a must.
- Expertise in Understanding Memory DFT is a Plus.
- Masters Degree with 4+ Years or Bachelors Degree with 5+ years
More Info
Job Type:
Industry:
Employment Type:
Key Skills
FinSim
MC analysis
nWave waveform viewer
XA
Memory Compilers
waveform viewer tools
Silicon Failures Analysis
Mentor schematic layout editor tools
XARA
Static and dynamic logic circuits
Split rail Power gating Architecture
layout design issues in sub nanometer regime
clocking scheme
Memory DFT
About Company
Skills:
Python Scripting, silicon debug, Circuit Simulation, nWave waveform viewer, Memory Compilers, XA FinSim, Silicon Failures Analysis, CMOS Circuit Design, XARA, HSIM, Hspice, Power gating Architecture
Skills:
Perl, Python, Tcl, Statistical Analysis, SPICE simulations, PVT corners, transistor-level simulation, yield optimization, Cadence Virtuoso, SRAM Memory circuit design
Skills:
Scripting, Memory Design, Synopsys, Flow automation, Analog Design, NVM design, IO standard cells, Foundation IP design, NVM technology macro architecture, Cadence
Skills:
top level verification, EDA tools for Cadence, block level routing, Floor Planning, layout dependent effects, EM IR quality checks, macro level assembly, CMOS integrated circuits