Develop and execute verification plans for SoC/ASIC/IP designs, including defining strategy, writing test plans, and architecting scalable verification environments.
Build and enhance UVM-based verification environments, ensuring reusability and maintainability of drivers, monitors, scoreboards, and checkers.
Perform constrained-random verification, analyze coverage metrics, and drive coverage closure with a strong emphasis on structured debugging and root-cause analysis.
Collaborate closely with RTL designers, firmware teams, and cross-functional partners to identify, debug, and resolve complex issues, demonstrating strong teamwork and communication.
Review design specifications, clarify requirements with stakeholders, and contribute to architectural discussions with a problem-solving mindset.
Job Conditions:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields.
4+ years of experience in ASIC/SoC/IP functional verification.
Strong proficiency in SystemVerilog and UVM methodology, with proven experience building robust verification environments.
Solid understanding of RTL design (Verilog/SystemVerilog) and ability to reason about design behavior when debugging complex issues.
Demonstrated ability to independently diagnose and resolve challenging verification or RTL issues using a systematic problem-solving approach.
Excellent teamwork, communication, and cross-functional collaboration skills.
Familiarity with Linux environments and scripting languages (Shell/Python).
Preferred Qualifications
Background in verifying high-speed interfaces such as PCIe, USB, DDR, Ethernet, or other subsystem-level IPs.
