Senior Digital IC Design Engineer(SoC)

We are seeking a highly motivated Digital IC Design Engineer to join our ASIC/SoC design team.

The successful candidate will participate in RTL design, verification, timing closure, and IP/SoC integration for display and multimedia applications. Strong teamwork, problem-solving skills, and experience with modern digital design flows are essential.

Key Responsibilities

Develop and implement RTL (Verilog/SystemVerilog) for digital blocks and modules.

Create and execute comprehensive functional verification plans using simulation and UVM methodologies.

Perform synthesis, static timing analysis (STA), and work with backend teams for timing closure.

Integrate IPs and subsystems into SoC designs; perform block-level and top-level verification.

Collaborate with architecture, analog/mixed-signal, DFT, and validation teams to meet product specifications.

Debug silicon bring-up issues and support post-silicon validation and bug fixes.

Prepare design documentation, design reviews, and technical presentations.

Optimize designs for area, power, performance, and testability.

Mentor junior engineers and contribute to process and toolflow improvements.

Requirements:

Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or related fields.

Minimum 3 years professional experience in digital IC/ASIC/SoC design.

Proficiency in Verilog or SystemVerilog for RTL design.

Experience with simulation tools (e.g., ModelSim, VCS) and verification methodologies (UVM preferred).

Familiarity with synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus), STA tools (e.g., PrimeTime), and constraint writing (SDC).

Strong understanding of digital design fundamentals: timing, pipelining, FSMs, CDC techniques, and reset strategies.

Demonstrated debugging skills and experience with waveform analysis.

Good scripting skills (Python, TCL, or Perl) for automation.