Senior Design Verification Engineer
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Location: Hyderabad / Bangalore / Remote
Experience: 5-12 Years
Employment Type:
Full-timeAbout The Role: We are looking for a highly skilled Design Verification Engineer with strong expertise in PCIe Protocol (Gen5 / Gen6) to join our high-speed interface IP / SoC verification team.
You will be responsible for verifying cutting-edge PCIe controller and PHY designs for next-gen data center and AI/ML SoCs.
Key Responsibilities:
Own verification of PCIe Gen5/Gen6 Controller IP (Root Complex / End Point / Dual Mode).
Develop SystemVerilog / UVM based verification environment from scratch and maintain existing TB.
Understand PCIe architecture and verify features like:Transaction Layer, Data Link Layer, Physical LayerFLIT Mode (Gen6), PAM4 Signaling, FEC, L0p, L1 PM SubstatesFlow Control, VC, QoS, Ordering, Completion HandlingLTSSM, Link Training, Equalization, Lane MarginingPower Management, SR-IOV, ATS, PASID, DOE, IDE (Security)PCIe Error Injection and Error Handling (AER, ECRC, Poisoned TLPs)Develop test-plans, coverage-plans, assertions (SVA) and functional coverage for Gen5/Gen6 features.Run regressions, debug failures with designers and drive to closure - 100% code & functional coverage.Work closely with Design, Architecture, and Firmware teams.Expertise in PIPE Interface verification (PIFP, 64b/128b/256b).Experience with Protocol Analyzers, LeCroy / Keysight Exercisers is a plus.
If You Are Intrested Or Any Known Candidates Are There ,Please Share Me Resumes to Below Mentioned Mail ID: [Confidential Information]
Job ID: 153517309
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog
Skills:
bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components
Skills:
Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping
Skills:
C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling
Skills:
Verilog, Scripting Languages, Verification Tools, VHDL, Uvm, formal verification, Simulators
