Senior Design Verification Engineer

Navii is an AI recruiter, running this search on behalf of Proxelera.

HERE'S HOW IT WORKS

Rather than your resume sitting in a queue, you have a conversation with Navii about your experience and what you want next. What you say reaches Proxelera's hiring team in your own words. It is a required step, and there is nothing to schedule.

NEXT STEP

A conversation with Navii about this role:

https://app.heynavii.ai/careers/verification-engineer-7e701210

ABOUT PROXELERA

Proxelera builds chip, systems, and software solutions for global leaders—and right now we need two strong verification engineers to keep engineering output moving without slip-ups. If you've spent years turning complex specs into coverage-driven, assertion-rich verification that actually finds bugs (and helps teams ship faster), this is your seat.

The Work

• Own functional verification for complex ASIC/System-on-Chip designs, end-to-end from early verification planning through tape-out readiness.

• Build and maintain functional verification environments using SystemVerilog + UVM.

• Drive coverage-driven verification using functional coverage, SVA assertions, and coverage closure strategies.

• Debug hard failures by triaging root cause across stimulus, DUT behavior, and environment issues.

• Use industry-standard simulators such as Questa or VCS to reproduce issues, validate fixes, and ensure verification completeness.

What You'll Need (Must-Haves)

• 8–10 years of hands-on experience in functional verification.

• Strong SystemVerilog and UVM expertise.

• Experience with functional coverage, assertions (SVA), and coverage-driven verification.

• Strong debugging and problem-solving skills in verification projects.

• Experience with Questa or VCS.

• Evidence of complete full-chip design-cycle experience—from design concept/early verification planning through tape-out handling of complex verification assignments.

• Full-chip experience must reflect ownership beyond IP/block-level verification (IP/block-only exposure is not sufficient).

Even Better If

• Experience with MIPI, DDR4/DDR5, and/or AMBA protocols (AXI4, AXI4-Lite, AXI4-Stream).

• Familiarity with VIP-based verification environments.

• Exposure to FPGA/Vivado-based IP verification flows.

Who Thrives Here

• You enjoy being accountable for verification quality—especially when timelines are tight and the design is complex.

• You're comfortable working across teams and locations, and you communicate clearly about what's working, what's blocked, and what you're doing next.

• You think in systems: not just make the test pass, but make the verification strategy catch the right failures.

• You like building reusable verification assets (environments, checks, coverage) that make future projects faster.

The Team

You'll be joining a delivery-focused engineering setup at Proxelera, supporting active work across verification and physical design output so projects don't slip. The team is built for multi-site execution, with engineers and design centers across India and the USA—so you'll collaborate with people who care deeply about throughput and engineering rigor.

Comp, Logistics and Benefits

• Location / Work mode: Bangalore, Onsite (all 5 days)

• Open roles: 2

• Compensation: The hiring team will share compensation details directly.

Benefits will be shared during the hiring conversation.

Non-Traditional Backgrounds

If your verification experience spans multiple protocol-heavy domains (and you can show how you drove coverage and debug to closure), we'd still like to hear from you.