RTL Design Engineer
RTL Design Engineer
Cyient- Posted a month ago
- Over 100 applicants have applied
Job Description
- Develop RTL designs using Verilog/SystemVerilog based on architecture specifications.
- Define and implement digital micro-architecture for SoC/IP blocks.
- Design and integrate modules related to:
- Motor Control Systems
- Industrial Communication Interfaces
- Embedded Controllers
- DMA, Interrupt Controllers
- GPIO, Timers, PWM Modules
- UART, SPI, I2C, CAN, Ethernet Interfaces
- Perform RTL coding, linting, CDC and quality checks.
- Analyze architecture specifications and convert them into RTL implementation.
- Support functional verification teams during simulation and debug activities.
- Collaborate with DFT teams for scan insertion and testability requirements.
- Work with Synthesis and Physical Design teams to close implementation issues.
- Participate in RTL reviews, design reviews, and code reviews.
- Prepare RTL documentation and design specifications.
More Info
Key Skills
linting
Motor Control Systems
DMA Interrupt Controllers
Ethernet Interfaces
Industrial Communication Interfaces
GPIO Timers PWM Modules
RTL documentation
RTL reviews
code reviews
Digital micro-architecture
About Company
Skills:
C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator
Skills:
Usb, Pcie, Verilog, Test Plans, Ethernet, floorplanning, Area optimization, RTL, systemverilog, Timing Closure, Synthesis, High-speed protocols, SERDES, Micro-architecture, ASIC Design, Silicon bring-up, Digital Design
Skills:
rtl development , static timing analysis, Verilog, Digital Signal Processing, LINT, Synthesis, Debug, LEC, Simulation, Matlab modeling, FPGA prototyping
Skills:
Verilog, Python, Synopsys, Cadence Tools, performance modeling tools, arithmetic units, accelerators, memory hierarchies, low-power design techniques, bus architectures
Skills:
catapult , Vcs, Ecos, Verilog, System Verilog, spyglass, LINT, Timing Analysis, Synopsys DC, cdc, Rtl Design, Verdi, VHDL, Stratus, Xcellium, SDC, Dft, Magillem, low power design methodologies