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Job ID: 147258335
Skills:
Tcl, Python, Perl, routing, floorplanning, UPF, RTL-to-GDSII execution, Physical Verification, automated design methodologies, LVS closure methodologies, Ir, Placement, CTS, signoff, Sta, low-power design strategies, ECO flows, physical signoff, CPF, Synthesis, Si, EM analysis, DRC
Skills:
Python, Static timing analysis, Unix, Splunk, AI ML, Linux, Lsf, Bitbucket, Jenkins, Git, make, EDA Tools, GenAI, Convolutional Networks, CI CD process, SW development and debug tools, Design Verification, reinforcement learning, Graph Neural Networks, DesignSync, Dft, Design revision control, Power-aware flows
Skills:
Lsf, Unix, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, Python, GenAI, VLSI CAD, CI CD process, DesignSync, make, reinforcement learning, Design revision control, Dft, Design Verification, EDA Tools, Power-aware flows, Convolutional Networks, Graph Neural Networks
Skills:
ethernet ip , C, Fpga, Python, Rtos, Linux, ASIC, Communications Protocols, TCP-IP, Firmware Verification, Embedded Systems
Skills:
static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis