Tcl, Python, Perl, routing, floorplanning, UPF, RTL-to-GDSII execution, Physical Verification, automated design methodologies, LVS closure methodologies, Ir, Placement, CTS, signoff, Sta, low-power design strategies, ECO flows, physical signoff, CPF, Synthesis, Si, EM analysis, DRC

Python, Static timing analysis, Unix, Splunk, AI ML, Linux, Lsf, Bitbucket, Jenkins, Git, make, EDA Tools, GenAI, Convolutional Networks, CI CD process, SW development and debug tools, Design Verification, reinforcement learning, Graph Neural Networks, DesignSync, Dft, Design revision control, Power-aware flows

Lsf, Unix, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, Python, GenAI, VLSI CAD, CI CD process, DesignSync, make, reinforcement learning, Design revision control, Dft, Design Verification, EDA Tools, Power-aware flows, Convolutional Networks, Graph Neural Networks

ethernet ip , C, Fpga, Python, Rtos, Linux, ASIC, Communications Protocols, TCP-IP, Firmware Verification, Embedded Systems

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Embedded Software, Rtl Design, Technical Specifications, IP selection strategies, Verification

Pcie, Verilog, Ethernet, Prototyping, Python, Scripting, Tcl, UCIe chiplet interconnects, AI tools, cdc, area optimization, Emulation, systemverilog, high-speed IO protocols, Rtl Design, formal verification, RDC, LINT, Timing Closure, silicon bring-up, CXL, micro-architecture, power efficiency

needs assessment , Ms Office, Optioneering, Infoworks ICM, Urban drainage modelling, Model verification, Waste water modelling, Gis Software