Hardware Acceleration Reference Model R&D Engineer

1. Responsible for developing and maintaining NPU emulators including ISS and Cycle-Accurate Model 2. Responsible for developing and maintaining compiler IR-based front-pass implementation for functional verification 3. Responsible for connecting with the chip verification team and providing reference models and test cases.

1. Solid foundation of computer processor architecture, familiar with the basic working principles of modern processors and instruction set ISA, etc. 2. Understand the implementation principles of processor simulators 3. Proficient in related programming languages such as C/C++, assembly and Python language 4. Good oral and written communication skills, team work awareness and spirit, proactive work and strong sense of responsibility 5. Bachelor degree or above, more than 3-5 years of experience in developing underlying system software in related fields. Priority will be given to candidates with one of the following skill requirements: 1. Experience in simulator development for x86, Arm, RISIV, SPARC or other architecture processors 2. Experience in SystemC engineering 3. In-depth understanding of neural network calculation graph programs such as machine learning and deep learning.