Design Verification Talent

Early Applicant

8-10 Years

Job Description

IC Design house

MSEE +8 years of relevant experience. At least 3 years of digital verification, including test writing and verification of several products
Experience with the verification methodology such as UVM.
Develop integrated verification environment.
Verify designs with system verilog and system verilog assertion.
Develop and optimize verification flow and methodology.
Good knowledge of IC design flow.
Scripting experience using scripting languages like Perl and Python.
Experience with the verification methodology such as UVM.