Perl, Python, Tcl, Physical-Aware Synthesis, Logic Synthesis, PPA optimization, systemverilog, UPF management

Embedded Firmware, Verilog, Scripting Languages, System Verilog, DVFS, DCVS, power gating, clock gating, power management verification, UPF, C Language, reliability throttling

Ovm, Test and coverage plan, Coverage and scenario creation, Verification environment, Validation plan, Assertion checkers, VMM Test Harness, System Verilog HVL, Uvm

Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog