C, Perl, Verilog, Shell scripting, Python, Tcl, SVA, UVM assertions, systemverilog

Usb, Fpga, Pcie, Perl, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, test bench infrastructure, FPGA and emulation platforms, AMBA, transaction level modeling, AXI4

Keysight, Exercisers, LeCroy, PIPE Interface verification, Uvm, PCIe Protocol Gen5, systemverilog, Protocol Analyzers

Design Verification, ASIC Design, Verification Planning, systemverilog, Rtl Design

Tcl, Python, Perl, systemverilog, System Verilog Assertions, Emulation

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog