Key qualifications:
1. MS degree with EE or CS background
2. Familiar with SystemVerilog and Verilog
3. Exposure to OVM/UVM/VMM methodology
4. Exposure to constrained-random based verification environment
5. Exposure to create coverage model and drive coverage closure in including code/functional coverage.
6. Be able to develop a test bench from scratch
Preferred qualifications:
1. Familiar with IEEE 802.3 standard
2. Familiar with TCPIP protocol stacks
3. Familiar Ethernet Switch/Router/NAT
4. Familiar xDSL standards
5. Familiar with 802.11x standards
6. Familiar with SOC bus fabric and AXI/AHB/OCP bus protocols
7. Familiar SVA
8. Familiar Formal verification methodology
9. Perl/Python experience
Job descriptions:
1. Test plan creation
2. Develop testbench, test cases, reference model, coverage model and regression suite
3. Run RTL and gate level simulation, debug failures, manage bug tracking
4. Drive and achieve coverage closure
(MD17C0031)
