Static Timing Analysis (STA) Lead

We are seeking an experienced STA Lead with strong expertise in ASIC timing analysis and timing closure across block and/or full‑chip designs. The role requires deep understanding of STA methodologies, constraints, ECO flows, and signoff checks, along with hands‑on experience using industry‑standard EDA tools on advanced technology nodes.

Key Responsibilities

• Perform Static Timing Analysis (STA) at block‑level and/or full‑chip level using industry‑standard tools
• Develop, analyze, and validate timing constraints (SDC) including clocks, generated clocks, IO constraints, and exceptions
• Drive timing closure across synthesis, PnR, and signoff stages
• Analyze and resolve setup, hold, transition, capacitance, crosstalk, and logical DRC violations
• Work closely with Physical Design, Synthesis, and Clocking teams to fix timing issues using ECO techniques
• Perform signoff STA across multiple PVT corners and modes (functional, scan, low‑power, test)
• Review STA reports and provide actionable recommendations for design optimization
• Support ECO implementation and verification to meet timing and QoR targets
• Contribute to methodology improvements and automation using scripting (TCL / Perl / Shell)

Required Qualifications

• 7+ years of relevant experience in STA and timing closure roles
• Bachelor's or Master's degree in Electronics / Electrical / VLSI Engineering or related field
• Strong fundamentals of ASIC design flow and timing concepts
• Hands‑on experience with STA tools such as:

Synopsys PrimeTime / Tempus

Understanding of ICC2 / Innovus / Fusion Compiler timing interfaces

• Solid experience in multi‑clock, high‑frequency SoC designs
• Good understanding of PnR impact on timing (CTS, routing, ECOs)
• Proficiency in TCL scripting for STA automation and analysis