Staff Design Verification Engineer

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

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Job Description:

Summary

As a Staff Hardware Engineer in Design Verification, you will own verification strategy and execution for complex outoforder (OOO) processor and cache/memory subsystems. You will define methodology, lead testplan creation, and drive verification of speculative execution, memory ordering, and coherence features from architecture through tapeout.

Key Responsibilities

Verification Ownership

• Own verification of OOO core subsystems, e.g.:
• Frontend: fetch, branch prediction, instruction decode, rename.
• Backend: scheduler/issue queues, execution units, bypass networks.
• Retirement & recovery: ROB, commit, exceptions, interrupts, mispredict recovery.
• Memory subsystem: LSU, TLBs, MMU, L1/L2 caches, coherence, fences, atomics.
• Define verification strategy and test plans from ISA + microarchitecture specs, with emphasis on:
• Speculative execution, forwarding, hazards, and replay mechanisms.
• Memory consistency model (e.g. RVWMO, TSO) and ordering rules.
• Coherence/consistency interactions across multicore systems.
• Drive coverage closure (functional, code, assertion, and scenario coverage) to signoff criteria.
  

Testbench Architecture & Implementation

• Architect constrainedrandom, coveragedriven UVM testbenches for:
• OOO core pipeline (including scoreboards and scoreboarddriven checking).
• Cache/memory hierarchy, TLB/IOMMU, and coherence protocols.
• Develop reusable verification components: generators for OOO stress (backtoback branches, deep speculation, dependency patterns), monitors, scoreboards, and protocol checkers.
• Model reference behavior (ISA / memory model) for endtoend checking of:
• Instruction retirement,
• Register and memory architectural state,
• Fence and atomic semantics.
  

Formal & Assertionbased Verification

• Write and maintain assertions for key OOO properties, e.g.:
• No deadlock or livelock in issue/ROB/LSU.
• Correct flush/replay on branch mispredict, exception, and interrupt.
• Loadstore ordering and databypass correctness.
• Apply formal verification to targeted units (e.g. ROB, scoreboard, arbiters, FIFOs, coherence controllers, TLB state machines).
  

Debug & Quality

• Lead debug of complex OOO bugs:
• Subtle ordering violations, rare hazards, cornercase speculation issues.
• Coherence races, TLB edge cases, and PMP/privilege interactions.
• Work closely with RTL, microarchitecture, and performance teams to rootcause issues and refine designs.
  

Methodology, Infrastructure, and Leadership

• Evolve DV methodology to efficiently cover OOO behavior:
• Scenario libraries for stress (long dependency chains, mixed privilege, multithread/multicore).
• Memory model and coherence checkers integrated into the environment.
• Mentor junior DV engineers on OOO CPU verification, debug strategies, and best practices.
• Collaborate crossfunctionally with architecture, design, SW, and postsilicon teams to ensure endtoend coverage of CPU usecases and customer workloads.
  

Required Qualifications:

Education / Experience

• BS/MS/PhD in EE/CE/CS or related field.
• Typically 8+ years in ASIC/SoC/IP design verification, with significant experience on outoforder CPU or advanced core projects.
  
  

Technical Skills

• Strong expertise in System Verilog and UVM.
• Direct verification experience with OOO CPU microarchitecture, including several of:
• Instruction fetch, decode, rename, and register mapping.
• Issue queue / scheduler, physical register files, bypass networks.
• Reorder buffer, exception/interrupt handling, flush/replay.
• Loadstore unit, store buffer, speculative loads/stores, LR/SC and atomics.
• TLBs, MMU, page table walkers, and protection (e.g. PMP, virtual memory).
• Solid understanding of:
• Memory consistency models (e.g. RVWMO, TSO) and how they map onto hardware.
• Coherence protocols and cache hierarchy (L1/L2+, inclusive/exclusive, writeback).
• Handson experience with:
• Coveragedriven verification and coverage closure.
• Assertionbased verification (SVA).
• Debug tools and largescale regression environments.
  

Preferred / NicetoHave:

• Experience verifying multicore OOO systems and intercore coherence.
• Experience with formal verification of OOO structures (e.g. scoreboard, ROB, loadstore queues).
• Exposure to RISCV or ARM ISA and privilege specs, including virtualization and security extensions.
• Experience with performance verification or microarchitectural modeling (to crosscheck pipeline behavior).
• Proven track record of technical leadership on complex CPU or SoC projects (tapeouts, methodology ownership, crossteam initiatives).
  
  

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.