Job Description
We are building Terafab, a vertically integrated semiconductor factory at an unprecedented scale. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot.
Process engineering is where Terafab technology gets built, atom by atom, and plating fills the structures that connect the chip. You will develop and own electrochemical deposition processes across three distinct chip families: edge-inference processors, space-hardened chips for orbital satellites, and high-bandwidth memory. You'll control void-free fill, thickness uniformity, and grain structure while managing bath chemistry, current distribution, and seed layer interactions across extreme aspect ratios and feature sizes.
You should have deep expertise in electrochemical deposition, but be ready to work across core process domains such as seed layer deposition, metrology, and barrier integration as integration evolves. This is a highly hands-on role at one of the most ambitious fab programs in the world.
Responsibilities:
Develop and qualify electrochemical deposition (ECD) processes for copper damascene interconnect and through-silicon via (TSV) fill across all metal levels including metrology monitoring and defect inspection for bath health and process control Optimize plating bath chemistry, current density profiles, additive formulations, and annealing conditions for void-free, low-stress copper fill at aggressive aspect ratios Develop and qualify electroless plating processes for capping layers and barrier-free interconnect schemes (Co, Ru) as applicable to advanced node requirements Qualify plating tools from installation through production readiness, including bath conditioning, anode management, and process window qualification Analyze processes from a first-principles, physics-based approach to understand and manipulate mechanisms, not just recipes Lead root cause analysis, establish inline metrology and SPC control strategies, and drive systematic yield improvement Support 24/7 manufacturing operations through rotations, on-call availability, and rapid response to critical production issues Drive next-generation plating chemistry and process development
Requirements:
BS or MS in Chemical Engineering, Materials Science, Electrical Engineering, Chemistry, or related technical field 5+ years of hands-on plating process engineering experience in a semiconductor fab, especially <7nm in a logic, memory, or foundry environment Deep experience with ECD tool qualification (Applied Materials, Lam, or equivalent), copper plating process development, and process of record (POR) establishment at advanced nodes Proficiency with plating metrology tools: film thickness measurement, defect inspection, TEM, XRF, resistivity measurement, and electrochemical analysis Strong DOE skills and statistical analysis capability (JMP, Python, or R) Ability to work closely and proactively across lithography, etch, thin films, integration, and equipment engineering teams
