Responsibilities
1. Responsible for the front-end/back-end verification of the company's chip projects, mainly focusing on SoC and system verification 2. Responsible for the formulation of verification plans, environment construction, incentive generation and coverage analysis, supporting software and hardware collaborative verification 3. Responsible for the development and maintenance of verification environments and processes.
Qualifications
1. Bachelor degree or above in microelectronics, computer and other related majors, 3 years or more of verification experience, tape-out experience is preferred 2. Familiar with chip development/verification process, proficient in verification-related EDA tools, proficient in mainstream verification methodologies such as UVM 3. Proficient in SystemVerilog hardware design language, familiar with one or more of the C/C++/SystemC modeling languages, and familiar with Python/Perl scripting language 4. Able to independently build a verification platform to complete IP subsys/SOC level verification, test point decomposition, and code/functional coverage analysis. Priority will be given to those who have one/more of the following verifications: 1. Experience with ARM/RISCV/DSP processors 2. Familiar with commonly used interconnect buses such as AMBA, MIPI protocols 3. Familiar with commonly used IPs, such as USB/PCIE/DDR/UART/SPI/I2C/SDIO/EMMC, etc. 4. Familiar with image/audio/video codec services, such as ISP/VEDIO codec, etc. 5. Familiar with high-speed interface Serdes/Phy protocols 6. Have experience in FPGA prototype verification/Emulation verification 7. Have experience in back-end netlist simulation/DFT simulation 8. Have experience in AI reasoning/training verification 9. Have experience in Low power verification.
