Job Project:
1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs.
2. Responsible for Physical Design flow research, development and automation.
Working location: Southern Science Industrial Park - Tainan Park
Requirements:
1. College degree or above 2. Familiar with IC back-end design process, relevant APR experience is preferred.
3. Interested in developing and promoting Physical Design Flow.
4. Familiar with related fields Tools (Astro, Encounter, IC Compiler) are preferred
5. Programming skills (TCL, Perl, C/C++) are preferred.
