SOC front-end design engineer (IP+SOC)-Data (Hangzhou)

1. Carry out IP module front-end design and SOC Integration according to the overall chip design requirements 2. According to the module specification requirements, determine the software and hardware division with the software, and complete the RTL design of the digital circuit module (including DFT), including circuit synthesis, timing check (Timing Check), functional verification, Formal Verification, simulation, etc. 3. Module-level power consumption, area, and performance analysis 4. Provide necessary support for back-end design. After the back-end design is completed, perform Post Layout Simulation 5. Participate in chip testing and debugging.

1. 5-year undergraduate degree in electronics, microelectronics, computer and other related majors, a master's degree or above and 3 years of SOC front-end design work experience 2. Relevant experience in digital integrated circuit front-end RTL design familiar with programming tools such as Verilog/SystemVerilog 3. Familiar with ARMV8 system architecture experience in developing 64-bit ARMSOC 4. Familiar with digital IC design process, proficient in EDA tools such as Synopsys/Cadence/Mentor 5. Understand DV/SV/UVM verification methodology proficient in using Linux/Unix operating system, familiar with Scripts languages such as Tcl/Perl/Python 6. Work seriously and responsibly, have good communication and learning skills, strong English reading and writing skills, and good teamwork spirit.