Work item:
1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs.
2. Responsible for Physical Design flow research, development and automation.
Requirements:
1. Graduated from a university or above in electrical engineering and information related departments
2. Familiar with IC back-end design process, with relevant APR experience
3. Interested in the development and promotion of Physical Design Flow.
4. Familiar with related tools (Astro, Encounter, IC Compiler) is preferred
5. Programming ( TCL, Perl, C/C++) ability is preferred.
