Search by job, company or skills

SoC Design Verification Manager

8-10 Years
SGD 12,000 - 15,000 per month
  • Posted 20 days ago
  • Be among the first 10 applicants

Job Description

Our client, a Singapore-based IC design house specializing in MCU, BMS, BLE, and TPM chip solutions for consumer electronics, automotive, industrial, and IoT applications, is seeking a qualified candidate to join their team as:

SoC Design Verification Manager

Scope

Lead a verification team developing state-of-the-art methodologies - from UVM and C co-simulation to mixed-signal and formal verification.

Responsibilities

. Lead the verification team's planning and execution across the SoC development cycle, managing risks and priorities to hit milestones

. Mentor and coach team members, supporting their technical growth and career development

. Develop verification plans and strategies that translate design specs into measurable coverage goals

. Architect and maintain scalable, reusable UVM/SystemVerilog testbenches

. Partner with design and project teams to resolve issues and keep projects on track

. Drive functional and code coverage analysis to close verification gaps ahead of tape-out

. Improve verification processes, methodologies, and tooling to boost team efficiency

. Participate in design/verification reviews, surfacing issues early

. Stay current on emerging verification trends, including formal and AI-assisted methods

Requirements

. Bachelor's, Master's, or PhD in EE, CE, CS, or related field

. 8+ years in design verification with strong SystemVerilog/UVM experience across SoC or IP projects 3+ years in people management

. Deep knowledge of digital logic, SoC architecture, and microarchitecture

. Proficient in simulation-based verification (UVM, SystemVerilog) able to architect scalable testbench environments

. Knowledge of low-power verification (power intent, power-aware simulation)

. Knowledge of mixed-signal and HW/SW co-simulation techniques

. Knowledge of gate-level simulation for timing and post-synthesis validation

Preferred

. Full verification cycle experience, planning through tape-out

. Hands-on experience building testbench architectures from the ground up

. Experience managing teams of 20+ engineers

EA Personnel Registration No: R1106329

EA License No: 12C6254

More Info

Job Type:
Industry:
Function:
Employment Type:

Job ID: 150989285

Beware of Scammers

We don’t charge money for job offers