Responsibilities
1. Connect with the demander, dismantle the systemic requirements and convert them into achievable technical specifications at the SoC architecture level 2. Participate in the top-level design of the SoC architecture and be responsible for writing SoC Top specification documents 3. Participate in the IP selection, specification definition and architecture design of each subsystem of the SoC to ensure efficient collaboration between subsystems 4. Responsible for the unified address space and access relationship planning of the SoC to meet the data interaction needs of each subsystem 5. Responsible for the RAS architecture design of the SoC to meet the system-level reliability index requirements organize discussions on other architecture issues across subsystems within the SoC, and be responsible for the design of related SoC top-level solutions 6. Participate in the design of SoC top-level integration, performance tuning, power consumption analysis and other solutions participate in software and hardware collaborative architecture discussions, and be responsible for the design of related SoC hardware solutions.
Qualifications
1. Bachelor degree or above in microelectronics, computer and other related majors, 5 years or more of SoC architecture/design experience 2. Familiar with SoC architecture (such as the industry's mainstream AI chip architecture, etc.), those with high-performance or advanced process SoC architecture experience are preferred familiar with CPU architecture (such as X86, ARM, RISC-V, etc.), and those with CPU architecture/design experience are preferred 3. Familiar with NoC architecture design, those with cloud chip NoC architecture/design experience will be preferred familiar with high-speed interface protocols such as DDR/PCIe/Ethernet/D2D, and those with high-speed interconnection architecture/design experience will be preferred 4. Understand clock reset design, and those with SoC top-level integration experience will be preferred understand the middle and back-end and packaging and testing processes of chip design, and those with relevant project experience will be preferred 5. Have a certain understanding of mainstream AI algorithms, and experience in mapping AI algorithms to SoC data flow projects will be preferred have a certain understanding of system software, and have experience in software and hardware co-design will be preferred 6. Have strong system analysis and problem-solving capabilities.
