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Job Descriptions
This role will own SI/PI methodology and design quality for high-speed product development, covering pre-layout exploration, post-layout verification, PDN optimization, and lab correlation. The engineer will work closely with EE, layout teams solve high-speed design challenges and provide design recommendations.
Job Responsibilities:
- Lead pre-layout signal simulation to optimize layout constraints and stack up design.
- Lead post layout signal simulation to evaluate high speed signal channel risk and provide design advice.
- Power integrity simulation and PDN optimization
- Review simulation results, identify design risks, and provide design recommendations to EE, layout, and product teams.
- Cooperate with EE/layout teams to improve design quality/efficiency.
Requirements
- Strong fundamentals of transmission lines RF and microwave theory.
- Detailed understanding of s-parameters and time domain vs. frequency domain analysis.
- Familiar with SI/PI tools(e.g. Keysight ADS,ANSYS HFSS/SIWAVE) and high speed interface such as PCIE,USB,SATA,DDR.
- Strong communication skills to quickly capture and understand design/product team needs and explain resolutions in crystal clear way.
- Team player to engage and work closely with different teams.
Job ID: 149112483
Skills:
Python, Ads, Seasim, SERDES, S2eye, HSIO design, DDR5 simulation, ANSYS AEDT automation, hfss, SIWAVE
Skills:
Ansys, Ads, ALLEGRO, Hspice, Seasim, Cadence, Pcb Design, Cable Design, ICAT, PCIe Gen6 GPU design
Skills:
Python, SERDES, VNA, DDR5 simulation, Ads, Seasim, S2eye, PNA measurements, HSIO design, ANSYS AEDT automation, hfss, SIWAVE
Skills:
Python, SERDES, VNA, DDR5 simulation, Ads, Seasim, S2eye, PNA measurements, HSIO design, ANSYS AEDT automation, hfss, SIWAVE
Skills:
Ads, Hspice, CADENCE SKILL, PCB layout tool Allegro, hfss, SIwave
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