Server FPGA/CPLD Design Leader/Engineer

Position Summary:

Own the logic behind system control for next-generation AI servers — from power sequencing and reset to full platform orchestration. You will develop and maintain CPLD/FPGA designs in Verilog, drive board bring-up, and collaborate across HW/BIOS/BMC teams to deliver robust, high-performance AI server and GPU cluster platforms.

Key Responsibilities

1. CPLD/FPGA Design

- Develop and maintain CPLD/FPGA designs using Verilog for server motherboard / backplane system control — power-on sequence, reset, GPIO, LED indication, and board management.

- Implement bus and protocol conversion / control logic, including DC-SCM, SGPIO, eSPI, and I2C.

2. System Control & Bring-up

- Define and implement hardware–firmware interfaces across CPU/GPU/ASIC platforms.

- Drive board bring-up, focusing on power sequencing, signal control, and system initialization debugging.

- Support component bring-up and platform validation with strong debugging and root-cause analysis.

3. Architecture & Planning

- Lead AI Server / Storage RFQ evaluation, including architecture definition and firmware/CPLD scope planning.

4. Collaboration & Ownership

- Collaborate with HW, BIOS, and BMC teams to resolve system-level issues and ensure design robustness.

- Own logic design quality, timing closure, and validation for firmware-related designs.

- Take full ownership of delivery schedule, design quality, and technical results.

What You'll Need

- Solid experience in CPLD/FPGA design (Verilog) for system control (power sequencing, reset, GPIO, board management).

- Familiarity with server / backplane architectures and protocols — I2C, eSPI, SGPIO, DC-SCM.

- Hands-on with board bring-up, timing closure, and validation.

- Strong debugging / root-cause analysis skills.

- Experience in AI server / storage / GPU cluster platforms preferred.

- Strong cross-functional communication and ownership mindset.

Why Join Us

- Work on cutting-edge AI Server / GPU cluster platforms, driving next-gen infrastructure.

- Hands-on ownership of CPLD/FPGA system control design — not just a support role.

- Exposure to complex system bring-up (power, reset, sequencing, multi-node coordination).

- Collaborate directly with top-tier AI / cloud customers and cross-functional teams.

- Grow into a system-level architect / technical leader in the AI infrastructure domain.