Responsible for the architecture design, RTL encoding (Verilog / System Verilog), and functional verification of digital control logic in 3D-NAND memory
Design a state machine (FSM) to manage complex NAND operation processes (such as Program, Read, Erase, Copy-back, Suspend/Resume, etc.)
Develop a command decoder and address/parameter parsing logic to ensure compliance with JEDEC and internal specifications
Implement high-precision timing control logic to accurately generate the internal timing signals required for various operations (such as tR, tPROG, tBERS, etc.)
Deeply involved in the physical layer and link layer logic implementation of ONFI (Open NAND Flash Interface) or Toggle Mode interface protocols, supporting DDR, NV-DDR, NV-LPDDR, and other modes
Collaborate with the analog / mixed-signal team to define array access timing, voltage switching windows, and read/write path control interfaces
Collaborate with firmware (FW) and system architecture teams to develop register maps, interrupt mechanisms, error handling strategies, and debug interfaces
Support UVM verification environment setup, provide Design for Testability (DFT) support, and participate in FPGA prototyping
Participate in chip bring-up, post-silicon debugging, and performance optimization to ensure products meet specification requirements.
Required Qualifications:
Education: Master's degree or above
Major: Microelectronics and Integrated Circuits, Electrical Engineering, Computer Engineering, or related fields
Other Requirements:
Minimum 5 years digital IC design experience, experience in NAND Flash or SSD controller projects is a plus
In-depth understanding of ONFI 4.x or Toggle 2.0/3.0 protocol specifications, with practical interface IP development or integration experience
Experience in control logic design under 3D-NAND or TLC/QLC architectures is a plus
Familiar with ECC control interfaces (such as LDPC/BCH engine scheduling and interaction)
Excellent cross-functional collaboration skills, able to communicate efficiently with simulation, firmware, verification, testing, and product teams to jointly develop technical solutions.
Experience with successfully tape-out and mass-produced memory chip projects is a plus.
