Job function:
1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out.
2. Responsible for physical design methodology research and development.
3. Cross site projects coordination and management.
Requirement:
1. MS with 5+ years of experience in Physical Design.
2. Familiar with Unix/Linux environment and scripts.
3. Familiar with ASIC design flow.
4. Familiar with Physical Design EDA tools.
5. Good communication and team working skills.
6. Experience in handling large scale SoC chip implementation is a plus.
