Company:
Qualcomm Semiconductor Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
We are looking for a Senior Engineer in Digital Test Engineering to support and drive SoC | Chiplet test program bring‑up and validation from NPI through high‑volume manufacturing.
This role emphasizes hands‑on ownership of structural test content (SCAN / ATPG / MBIST), with opportunities to work across functional, high‑speed, and characterization testing. The position focuses on debugging test issues, improving test efficiency, and enabling robust, scalable test solutions, particularly on advanced technology nodes.
You will work closely with DFT, Design, Yield, Reliability, Product, and Test Engineering teams, contributing to issue resolution, data‑driven decisions, and continuous improvement of test quality and cost.
Key Responsibilities
- Develop, bring up, and validate SoC | Chiplet test programs across NPI and high‑volume manufacturing stages.
- Debug and resolve issues related to coverage, test time, yield, and test escapes.
- Improve test efficiency and cost, including test time optimization and test flow simplification.
- Analyze test and yield data to identify trends, root causes, and improvement opportunities.
- Collaborate cross‑functionally with DFT, Design, Yield, Reliability, Product, and Manufacturing Test Engineers.
- Participate in cross‑region collaboration, driving timely issue resolution across global teams.
- Communicate technical findings clearly to peers and stakeholders, with appropriate level of detail.
Minimum Qualifications
- Bachelor's or Master's degree in Electrical / Electronic Engineering, Computer Engineering, or a related field.
- 4+ years of Test Engineering experience, with hands‑on involvement in SoC test program bring‑up.
- Experience in one or more of the following test areas:
- Structural test (ATPG, TDF, MBIST)
- Functional test
- High‑speed test
- Test‑related characterization
- High‑voltage stress
- Experience in one or more chiplet‑based or multi‑die products, including die‑to‑die (D2D) interfaces and associated test and yield challenges.
- Hands‑on experience with Advantest 93K or Teradyne UltraFLEX / iFlex test platforms.
- Proficiency in one or more programming or scripting languages (C++, VB, Java, Python).
- Experience using test or yield data analysis tools (e.g., O+, Data Power, Exensio).
- Exposure to test method or test library development, including development, validation, regression, and enhancements.
Preferred Qualifications
- Strong background in Structural Test Engineering, particularly SCAN / ATPG / MBIST.
- Experience working on System‑on‑Chip (SoC) | Chiplet products.
- Experience defining or executing chiplet test strategies, including:
- D2D interface coverage
- Multi‑stage test flows
- Yield issue root‑causing and resolution
- Collaboration with DFT, Design, Process, and Package Design teams
- Experience supporting test bring‑up or debug on advanced or leading‑edge technology nodes.
- Experience using data analysis tools such as O+, Exensio, JMP, or similar platforms.
- Experience mentoring or supporting junior engineers in a collaborative engineering environment.
- Interest or experience in AI‑assisted tools for test automation, workflow efficiency, or engineering data analysis.
- Hands‑on experience with version control systems (Git or SVN).
- Familiarity with issue tracking systems such as JIRA.
- Comfortable communicating in English, including participation in technical discussions and cross‑region collaboration.
Minimum Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
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