Senior Digital IC Design Engineer(Driver IC)

We are looking for a motivated Digital IC Design Engineer with a Master's degree and at least 3 years of hands-on experience in digital design for driver ICs (display driver or related products). The candidate will focus on RTL development, verification, synthesis, timing closure, IP integration, and silicon bring-up for driver-IC projects, collaborating with cross-functional teams to deliver high-quality, low-power solutions.

Key Responsibilities

Design and implement RTL (Verilog/SystemVerilog) for digital blocks in driver ICs (timing controllers, interface logic, gamma/LUT controllers, etc.).

Perform logic synthesis, static timing analysis (STA), and constraint (SDC) creation and maintenance.

Work closely with backend teams for placement & routing considerations and achieve timing closure.

Integrate digital IPs and collaborate on mixed-signal interfaces with analog teams.

Support FPGA prototyping and system-level bring-up for validation.

Debug pre-silicon and post-silicon issues; participate in failure analysis and propose fixes.

Optimize designs for area, power (low-power techniques), performance, and testability (DFT).

Produce design documentation, participate in design reviews, and present technical results.

Mentor junior engineers and contribute to process/toolflow improvements.

Requirements:

Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or related fields.

Minimum 3 years of professional experience in digital IC design, preferably involving driver IC or display-related projects.

Proficient in Verilog or SystemVerilog for RTL design.

Hands-on experience with synthesis tools (e.g., Synopsys DC, Cadence Genus), STA tools (e.g., PrimeTime), and SDC constraint writing.

Solid understanding of digital design fundamentals: timing closure, pipelining, FSMs, CDC, reset strategies.

Strong debugging skills and waveform analysis experience.

Good scripting ability (Python, TCL, or Perl) for automation.