Senior Design Verification Engineer
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Job ID: 141113941
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog
Skills:
bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components
Skills:
Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping
Skills:
C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling
Skills:
Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage
