Google welcomes people with disabilities.
Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in architecture, microarchitecture, or design in the following areas: DRAM PHY or memory controller.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in SoC system pre-silicon and post-silicon memory subsystem analysis, tuning and debugging.
- Experience in designing LPDDR PHY and joining post-silicon/max production debugging.
- Experience in improving memory system power efficiency.
- Experience in one or more of the following standards: LPDDR5, DDR5, DDR4, or HBM and understanding of LPDDR5/6 DRAM standards.
- Knowledge of LPDDR initialization processes, Dynamic Voltage and Frequency Scaling (DVFS), training procedures, and calibration sequences.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Within the Google Silicon Platform IP team, You will engage in collaborative efforts with hardware, DDPHY 3PIP, software, and power architects to establish memory architectures tailored for the Google Tensor System on Chip (SoC) and related offerings. In this role, the primary responsibility will be the specification of memory controller and DDRPHY architecture and micro-architecture to achieve performance and power efficiency. You will participate in the development of technologies for the SoC Platform IP, as well as the preparation and submission of patent applications.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Conduct concept studies and provide direction regarding new DRAM technology implementation, power optimization, and performance enhancement.
- Collaborate with analog and software architects to define tailored features aimed at improving power and performance, and to author comprehensive architectural specifications.
- Analyze SOC use cases in detail and optimize memory subsystem power consumption, particularly concerning the DDRPHY.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
