R&D IIP Simulation Engineer

Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world's largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.

We are seeking a highly motivated and talented R&D Engineer to join our team in developing advanced IC packaging technologies. This position offers an exciting opportunity to work on cutting-edge solutions, such as CoWoS (Chip-on-Wafer-on-Substrate), Fan-Out Wafer Level Packaging (FOWLP), and 3DIC (Three-Dimensional Integrated Circuits). The ideal candidate will have strong technical expertise and a passion for innovation in semiconductor packaging design and analysis.

Join us in shaping the future of advanced IC packaging technologies and contributing to groundbreaking innovations in the semiconductor industry. This role provides a unique opportunity to work in a dynamic environment, solve challenging engineering problems, and make a meaningful impact on next-generation packaging solutions.

Job Responsibilities:

1. Conduct risk assessments and provide mitigation plans for IC packages through simulation and experiment, interpreting experimental data and simulation to provide insights into material selection and design improvements.

2. Practice FEM and DOE in problem solving and path finding particularly on packaging. Conduct mechanical or thermal simulations using finite element analysis (FEA) techniques to evaluate and optimize packaging performance, and analyze stress, deformation, and heat dissipation characteristics to ensure reliability and efficiency of packaging designs.

3. Continuously improve simulation methodology, refine material modeling, and enhance script automation capabilities.

Job Qualifications:

1. Master's degree or above in Material Science, Physics, Chemistry, Mechanical, or a related engineering discipline.

2. Utilization of advanced CAE tools such as ANSYS Mechanical, ANSYS Icepack, Flotherm, and ABAQUS for simulation and analysis. Develop or compile finite-element pre- and post-processing application software to enhance simulation workflows and improve efficiency.

3. Strong technical problem-solving and analytical skills such as JMP DOE, Taguchi, Ford 8D, K-T method.

4. Excellent written and verbal communication skills to effectively collaborate with cross-functional teams and present technical findings with a growth mindset.

Fostering a global inclusive workplace reflects TSMC's core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.