We are seeking a highly skilled Software Engineer to join Zebu timing team in Synopsys.
Synopsys is uniquely positioned to offer the most complete verification solution in market today. ZeBu is the emulation platform of Synopsys verification flow, it's the industry's performance & capacity leader in Emulation.
As a Zebu backend R&D, we collaborate with cross-functional teams globally to analyze technical issues, develop the solution for requirements from customer and optimize Zebu QoR everyday.
R&D in timing team needs to learn Static Timing Analysis, timing graph generation and delay estimation techniques. We create a fast and accurate timer to optimize and sign-off runtime frequency in both Zebu and ProtoCompiler.
Requirements:
- Education Requirements
- MS (or above) in Electrical Engineering/Computer Science.
- Skills/Experience
- Good team player and communication skills.
- Good knowledge of proficient in C++, data structure and algorithm.
- B1 or above level English on reading/writing/listening/speaking (especially on discussing and documenting technical spec).
- Nice to have
- Familiar with STA and timer like PrimeTime.
- Familiar with RTL coding , chip design experience or verification env. architect experience,. Understanding big picture at the ASIC architectural and system level with experience on real block/soc verification experience .
- Good expertise on emulators/prototyping like Zebu/Palladium/Veloce/ProtoCompiler/Protium or FPGA compile/runtime/debug are preferred.
- Familiar with FPGA tools likes Xilinx Vivado/Vitis and Synopsys Synplify,
- Familiar with scripting language like Tcl/CSH/BASH/Python/Makefile/Perl.
- Experience on driver/FW FPGA development.
- Familiar with simulation tool like VCS/Verdi
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
