Job Objectives
- To develop III-V semiconductor etch, clean tech andLapping processes and capabilities aligned to company's technology and product roadmap and integrated with in-house manufacturing capabilities.
- Define process andequipment roadmap for photonics related Etch, Clean tech and Lapping processes.Support of new technology prototype process set up and demonstration. Transferof process to manufacturing counterpart upon maturity. Involve in new equipment selection, evaluation and start up.
Duties and Responsibilities
- Develop, optimize, and qualify dry etch (RIE/ICP) and wet etch processes for compound semiconductor device fabrication.
- Own and monitor etch-related FAB quality indices, including Line Yield, etch rate/uniformity, selectivity, profile control, and SPC.
- Lead troubleshooting of etch-related process excursions and drive root cause analysis and corrective/preventive actions (8D/CAPA).
- Manage process documentation and change control records for dry and wet etch process steps.
- Lead new etch process development and qualification activities for NPI/NPD projects, including evaluation of new chemistries and process recipes.
- Collaborate closely with Equipment Engineering on etch tool performance, preventive maintenance schedules, and chamber-to-chamber matching.
- Drive continuous improvement initiatives aligned with LEAN methodology.
- Set up and maintain control documentation and SPC records for etch processes train and guide technicians and operators.
- Support the evaluation and qualification of new etch equipment, chemicals, or outsourced FAB vendors.
- Prepare technical reports on analyses, findings, and project updates for management.
- Stay current with etch process technologies and participate in knowledge-sharing activities.
- Participate in special projects or task forces as assigned.
- Perform other reasonable duties as assigned.
Qualification Guidelines
Minimum Education
Bachelor Degree in Electrical Engineering, Materials Science, Applied Physics, Chemical Engineering, or a related discipline
Minimum Experience
Minimum 5 years of relevant experience in dry and/or wet etch process engineering within a semiconductor, photonics, optoelectronics, or compound semiconductor wafer fabrication environment preferred.
Specific Knowledge / Skills
- Hands-on experience with dry etch platforms (RIE/ICP-RIE) including gas chemistry selection (e.g., chlorine- or fluorine-based chemistries for III-V/dielectric etch), plasma power/bias tuning, and endpoint detection.
- Working knowledge of wet etch/wet bench processes, including acid- and solvent-based etchants, etch selectivity between III-V compound semiconductor layers (e.g., InP/InGaAsP/InGaAs), and undercut/profile control. Familiar with etch rate characterization, uniformity mapping, and surface morphology/roughness evaluation (e.g., via SEM or profilometry).
- Knowledge of chemical and gas safety protocols, including handling of hazardous/corrosive chemicals and pyrophoric gases where applicable.
- Competent in SPC, DOE, and 8D/root cause methodology. Good leadership and cross-functional communication skills.
- Experience with III-V compound semiconductor processes and photonics device fabrication is an advantage.
