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Experience: 8+ Years
About Tsavorite
Powering the next wave of AI infrastructure. Tsavorite builds next-generation AI compute systems for edge, on-prem, and data centre deployments. The company is developing a heterogeneous, chiplet-based architecture that combines custom AI Cores, ARM Application Cores, high-bandwidth memory, and the MultiPlexus™ scalable fabric to support inference, training, and emerging agentic AI workflows. Delivered through the Helix platform and TAOS software stack, Tsavorite has design centres in the US and India. Tsavorite's systems are designed to provide scalable performance, flexibility, and efficiency across modern AI workloads.
Job Summary
We are looking for an experienced Physical Design Engineer (8-14 Years) with strong expertise in RTL-to-GDS implementation, Cadence Innovus, advanced-node Block/SoC designs, and PPA optimization. Candidates should have hands-on System Verilog + Python/Perl scripting experience and a proven track record of delivering high-volume shipped products.
What You'll Drive & Bring to the Role
Required Qualifications
• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline with 8-14 yrs of work experience.
Why Join Us
Benefits
Job ID: 152333521
Skills:
Power Planning, Routing optimization, floorplanning, Placement, Debugging setup hold violations, Physical Verification, Physical Design ASIC implementation, Cadence Innovus
Skills:
layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs
Skills:
redhawk , Routing, Perl, Python, Tcl, SDC constraints, Design Compiler, CTS, primetime, Fusion Compiler, RTL-to-GDS implementation, Voltus, ECO implementation, Full Chip Physical Design, Synthesis, MCMM timing closure, Physical Design methodologies, EM IR analysis, Synopsys ICC2
Skills:
Perl, Python, Tcl, primetime, StarRC, Cadence Innovus, Synopsys ICC2
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology