Physical Design Engineer
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Job ID: 151931121
Skills:
Perl, Python, Tcl, Function eco creation, Timing Closure, Synthesis, Netlist quality check, formal verification, Constraints creation and validation, STA for hierarchical design, Flow automation development
Skills:
Perl, Python, Tcl, Function eco creation, Timing Closure, Synthesis, Netlist quality check, formal verification, Constraints creation and validation, STA for hierarchical design, Flow automation development
Skills:
layout verification , Tcl, DRC fixes, power analysis, place and route implementation, advanced technology nodes, Timing Closure, Cadence Innovus, lower power design, Synopsys ICC2
Skills:
Perl, Python, Tcl, Function eco creation, STA for hierarchical design, Constraints creation and validation timing budget, Develop and enhance entire timing closure flow from frontend pre-layout to backend post-layout, formal verification, Synthesis Netlist quality check, Implement chip partition and floorplan, Timing closure for both partition and full chip level, Flow automation development
Skills:
Makefile, Perl, Tcl, primetime, Fusion Compiler, Formality, LEC, Tempus, Physical Design, Cadence Genus, Voltus, Innovus, Calibre, Synopsys IC Compiler, block-level PNR, EM IR-Drop Crosstalk analysis tools, static timing analysis tools, PrimeRail
