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We are now looking for VLSI Physical Design Engineers in Hsinchu office, Taiwan. We utilize latest process technology, advanced EDA tools, and sophisticated design methodology. We always work on the most challenging designs, and push for performance limit.
What you'll be doing:
A role in physical design for NVIDIA GPU and Mobile chips.
Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention.
Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.
What we need to see:
BS in Engineering or Science or equivalent experience
Power user of EDA tools from Synopsys (ICC2/DC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus) or Ansys (Redhawk)
Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes
2+ years of experience in above areas
Ways to stand out from the crowd:
MS in Engineering or Science
Knowledge in FinFET technology, circuit design, and package design
Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre)
Proficiency in Perl, Python, TCL and Makefile scripts
Mellanox Technologies Ltd. was an Israeli-American multinational supplier of computer networking products based on InfiniBand and Ethernet technology.
Job ID: 144543297
Skills:
layout verification , Tcl, DRC fixes, power analysis, place and route implementation, advanced technology nodes, Timing Closure, Cadence Innovus, lower power design, Synopsys ICC2
Skills:
Perl, Python, Tcl, Function eco creation, STA for hierarchical design, Constraints creation and validation timing budget, Develop and enhance entire timing closure flow from frontend pre-layout to backend post-layout, formal verification, Synthesis Netlist quality check, Implement chip partition and floorplan, Timing closure for both partition and full chip level, Flow automation development
Skills:
Perl, Python, Tcl, Function eco creation, Timing Closure, Synthesis, Netlist quality check, formal verification, Constraints creation and validation, STA for hierarchical design, Flow automation development
Skills:
Makefile, Perl, Tcl, primetime, Fusion Compiler, Formality, LEC, Tempus, Physical Design, Cadence Genus, Voltus, Innovus, Calibre, Synopsys IC Compiler, block-level PNR, EM IR-Drop Crosstalk analysis tools, static timing analysis tools, PrimeRail