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Physical Design Engineer
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- Posted 10 days ago
- Be among the first 30 applicants
Job Description
Description
We are seeking an experienced Physical Design Engineer to join our team in India. The ideal candidate will have a strong background in physical design implementation and will be responsible for optimizing IC layouts to meet performance and power requirements.
Responsibilities
- Perform physical design implementation of integrated circuits (ICs) from RTL to GDSII.
- Develop and optimize physical layouts for performance, power, and area.
- Conduct design rule checks (DRC) and layout versus schematic (LVS) verification.
- Collaborate with design engineers to resolve issues related to physical design.
- Utilize EDA tools for various stages of the physical design flow, including synthesis, place and route, and timing analysis.
- Engage in design reviews and provide feedback to ensure adherence to design specifications.
Skills and Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 6-15 years of experience in physical design engineering or a related field.
- Proficiency in using EDA tools such as Cadence, Synopsys, or Mentor Graphics.
- Strong understanding of VLSI design principles and physical design methodologies.
- Experience with RTL synthesis and timing closure techniques.
- Familiarity with scripting languages such as Tcl, Perl, or Python for automation.
- Excellent problem-solving skills and attention to detail.
- Ability to work collaboratively in a team environment.
Bachelor Of Technology (B.Tech/B.E), Masters in Technology (M.Tech/M.E)
More Info
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Key Skills
About Company
Skills:
power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies
Skills:
Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog
Skills:
static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, Place And Route, low-power design techniques, Clock Tree Synthesis
Skills:
Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement
Skills:
power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation