Search by job, company or skills

Memory IP Architect / SoC uArchitect Executive Level

Memory IP Architect / SoC uArchitect Executive Level

Michael Page
15-17 Years
Not Disclosed
  • Posted 2 hours ago
  • Be among the first 10 applicants

Job Description

Memory IP Architect / SoC uArchitect

  • Lead next-generation memory architecture for AI, HPC, networking, and ASICs.
  • Drive product from concept through silicon while working with executive level.

About Our Client

Our client is a fast-growing semiconductor technology company focused on developing advanced silicon solutions for data-intensive applications. The organization combines deep expertise in system architecture, IP development, and custom SoC design, serving customers in emerging high-performance computing, AI, and networking markets.

Job Description

  • Define the architecture, specifications, and roadmap for advanced memory IP and SoC memory subsystems.
  • Drive system-level memory strategies covering bandwidth, latency, power efficiency, scalability, and total cost optimization.
  • Architect solutions utilizing technologies such as DDR5, LPDDR5X/LPDDR6, HBM3E/HBM4, SRAM, cache hierarchies, and memory coherency frameworks.
  • Conduct architectural exploration, performance analysis, and modeling using software-based simulation environments.
  • Partner closely with RTL, verification, DFT, physical design, packaging, firmware, and software teams to ensure successful implementation.
  • Participate in customer-facing technical discussions, design reviews, and long-term product planning.
  • Support silicon bring-up activities, debug efforts, and post-silicon performance optimization.

The Successful Applicant

  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
  • 15+ years of semiconductor industry experience with significant architectural ownership.
  • Demonstrated success delivering complex SoC, memory controller, or memory IP products from definition through production silicon.
  • Strong expertise in multiple areas, including:
    • DDR5, LPDDR5X, and LPDDR6
    • HBM3E and HBM4
    • SRAM and cache architecture
    • Memory controllers and PHY technologies
    • Memory coherency protocols
    • AI accelerator or HPC system architecture
  • Hands-on experience with architectural modeling and simulation using C/C++, SystemC, Python, or related tools.
  • Strong communication, leadership, and cross-functional collaboration skills.
What's on Offer

  • Competitive executive-level compensation package with performance-based incentives.
  • Opportunity to shape cutting-edge memory technologies and future silicon platforms.
  • Global collaboration across engineering teams in multiple regions.
  • High visibility with senior leadership and direct impact on product strategy.
  • Career growth within a rapidly expanding semiconductor organization focused on next-generation computing solutions.

Quote job ref: JN-102026-7120147

More Info

Job Type:
Industry:
Function:
Employment Type:

Key Skills

HBM4

memory coherency protocols

LPDDR5X

PHY technologies

HPC system architecture

HBM3E

cache architecture

DDR5

LPDDR6

About Company