Job Description

Summary: Seeking a highly skilled and experienced Lead STA Engineer to lead and execute static timing analysis for complex semiconductor designs, ensuring timing closure and performance targets are met. This role involves guiding a team, developing methodologies, and collaborating with design and verification teams to deliver high-quality products.

Job Qualification

Master's degree or Bachelor's degree in Electronics/ Electrical Engineering, Computer Engineering, or a related field.
7+ years of hands-on experience in static timing analysis for complex ASIC/SoC designs.
Experience of Multi mode timing constraint development, execution, and final timing signoff for advanced technology nodes
Proven experience leading STA efforts for multiple successful tape-outs.
Expertise in industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).
Strong understanding of digital design fundamentals, clocking architectures, and low-power techniques
In-depth knowledge of timing constraints (SDC) and their application.
Proficiency in scripting languages such as Perl, Python, or TCL.
Strong communication and interpersonal skills, with the ability to collaborate effectively in a global team environment.
Work closely with Architects,Front End,DFT and the PD team to understand design,clocking,timing ,Requirements and lead the writing constraints and closing timing activities

Key Responsibilities

Constraint Development: Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes.
Timing Signoff: Perform exhaustive timing analysis across multiple corners and modes (MCMM), adhering to process, voltage, and temperature (PVT) variations.
Violation Debugging: Debug and resolve setup, hold, transition, and path-based violations (PBA).
Optimization & ECO: Drive timing closure by generating and evaluating timing Engineering Change Orders (ECOs).
Cross-functional Collaboration: Partner with RTL, physical design, and DFT teams to ensure robust timing integration and refine timing models.
Tool & Flow Automation: Develop and support implementation flows using industry-standard Electronic Design Automation (EDA) tools and improve script-based automation.
Drive a small team of STA engineers.
Should be able to do IP level synthesis.

More information about NXP in India...

More Info

Job Type:

Permanent Job

Industry:

Semiconductor Manufacturing

Function:

Semiconductor

Employment Type:

Full time

Key Skills

low-power techniques

Electronic Design Automation EDA tools

digital design fundamentals

Multi mode timing constraint development

STA tools

synopsys primetime

Cadence Tempus

ASIC

clocking architectures

timing constraints SDC

timing signoff

static timing analysis

About Company

Last Updated: 29-09-2026 04:07:28 AM

4-12 yrs

Bengaluru, India

Skills:

Static Timing Analysis (STA), Timing ECO strategies, Full-Chip Timing Closure

6-12 yrs

Bengaluru, India

Skills:

synopsys primetime , Perl, Static Timing Analysis, Python, Tcl, Timing exceptions, OCV, ASIC implementation, Full-chip STA, Timing sign-off, Timing Closure, SDC, MMMC, POCV, Si, Physical design flow, AOCV