IP Verification Engineer-Data (Hangzhou)

1. Build a UVM verification environment 2. Be proficient in verification methodology and implement an automated and reusable verification environment 3. Responsible for formulating verification plans and completing coverage collection to ensure high-quality delivery 4. Be familiar with and perform performance verification, power consumption-aware simulation, RTL/FW co-simulation and GLS simulation 5. Assist designers to debug design defects and be responsible for the analysis of regression results 6. Responsible for improving and perfecting the verification process.

1. 2-5+ years of relevant chip verification experience 2. In-depth understanding of UVM, System Verilog, Makefile, Perl, Python, C/C++ applications 3. In-depth understanding of AMBA ACE-lite4/5 protocol, SMMU, IO Coherency, Scheduler 4. Experience with chip interconnect protocols CXL and CCIX is preferred experience with NVMe, SR-IOV, S-IOV, and compression algorithms is preferred 5. Have strong English reading, writing and communication skills 6. Have a self-driven, result-oriented, milestone-driven working style, and a good team spirit.