Hardware Acceleration Compiler Framework R&D Engineer

1. Responsible for the development of the overall compilation framework 2. Responsible for the development of compilation optimization functions such as instruction scheduling, storage allocation, and parallel scheduling 3. Responsible for the development and optimization of the model performance Auto-tuning function 4. Responsible for the development of the Runtime module.

1. Have an in-depth understanding of deep learning frameworks and software stacks 2. Be proficient in related programming languages such as C/C++, assembly, and Python 3. Have the ability to proactively learn, quickly solve problems, and be self-motivated. The following are bonus points: 1. Have experience in MLIR development product experience related to multi-thread development 2. Familiar with computer architecture and parallel computing 3. Understand compiler and code optimization technology, familiar with intermediate representations such as TVM/XLA, and have relevant development experience 4. Have an in-depth understanding of commonly used deep learning frameworks, including but not limited to TensorFlow/PyTorch, MXNet 5. Have in-depth LLVM and C++ development experience have experience in the development of quantitative tools for AI acceleration hardware 6. Have development and evaluation experience related to GPU, FPGA or AI chips.