(??) DRAM Design Verification Engineer

() DRAM Design Verification Engineer ./CAD//FAE

1. Designing and developing behavioral models for both standard and customized DRAM
2. Building and maintaining verification environments (TestBench) to ensure design quality and functional correctness
3. Participating in customer specification discussions, with the responsibility to thoroughly understand the specifications in advance to support behavioral model development

(.539)

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1. Familiar with SystemVerilog with hands-on coding experience
2. Familiar with RTL coding and synthesis flow
3. Experience with DRAM behavioral specifications is a plus
4.Familiarity with scripting languages such as Tcl, Perl, or Python is a plus

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