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Director - STA
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Director - STA
NXP Semiconductors India Private LimitedFresher
- Posted 9 hours ago
- Be among the first 10 applicants
Job Description
Timing Analysis activities for MPU SoCs.
- Expertise in developing, implementing and verifying STA constraints
- Expertise in efficient closure of Subsystem as well as SoC-level timing
- In-depthknowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & Route
- Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes
- Contribute to timing flow and methodology improvements
- Collaborate with members of a global design team to complete large SoC (system-on-chip) projects.
Cross functional collaboration:
- Partner with Architecture and RTL teams to influence early design decisions
- Ability to coordinate with all aspects of SOC design functions, including RTL, DV, DFT, EDA vendors, DTCO while setting technical direction for the team
- Work with methodology teams to continuously improve flows and processes
Key Challenges:
- Demonstrate strong expertise in all aspects of timing analysis for a wide variety of designs, from constraint generation and verification to full-chip timing closure across all modes and scenarios.
- Deep understanding of advanced topics such as crosstalk, noise, OCV, timing margins. Familiarity with Clock specs, jitter, IR drop, spice analysis.
- Experience working with multi-site teams for execution is a must
Job Qualifications:
- BS or MS in Electrical or Computer Engineering
- 15+ years of experience in Physical Design for complex SoCs
- Experience with at least 3 years of STA Lead roles
- Excellent communication skills, both oral and written
- Innovate and adapt to the rapid use of AI and agents in STA & PD domains
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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Key Skills
methodology improvements
IR drop
crosstalk noise
timing flow
STA constraints
Clock specs
spice analysis
OCV timing margins
Floor-planning
