Work item:
Verification for a CPU design project, which includes:
. Responsibility for test plans, testbench documentation and implementation.
. Use SystemVerilog language, SVA and UVM methodology for block and top level verification.
. Apply formal property checking/formal verification methodologies
. Understanding of the fundamentals of computer architecture
Requirements:
1. Master degree or above electrical machinery, electrical machinery and control, information engineering, electronics Graduated from relevant departments.
2. Relevant work experience is preferred.
(MD1570002)
